JPMontero_Intel, I'm trying to understand your message...
In the datasheet (Intel ® Quark™ SoC X1000 Datasheet, page 38) I can read:
"The SoC also features a 512 Kbyte on-die embedded SRAM (eSRAM) that can be
configured to overlay regions of DRAM to provide low latency access to critical portions
of system memory."
and later (page 127):
"The Host Bridge contains an interface to 512KB of on-chip, low latency, embedded
SRAM (eSRAM). The eSRAM memory may be used as either 128 x 4KB pages, or in
block mode as a single contiguous 512KB block page. The eSRAM pages may be
mapped anywhere in the physical address space as a DRAM overlay."
Both "per page" and "block" mode seem not to differ much...
The datasheet seems to say: "eSRAM is not available directly in physical address, but can be configured to overlay (steal) some physical addresses of DRAM (either a 512kB block or chosen 4kB pages)". And it seems to offer performance gain.
Could you elaborate a little more and point me to some relevant part of the datasheet and/or "Intel ® Quark™ SoC X1000 UEFI Firmware Writer’s Guide" to get a better understanding?
Regards,
Krzysztof